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AN11130 bias module for 50 v gan demonstration boards rev. 1 ? 8 december 2011 application note document information info content keywords gan, bias abstract this application note describes a bias controller module for gan hemt rf power transistors. it provides constant quiescent drain current with temperature, special bias and po wer sequencing, and overcurrent protection.
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 2 of 14 contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com nxp semiconductors AN11130 bias module for 50 v gan demonstration boards revision history rev date description v.1 20111208 initial version
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 3 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 1. introduction gan hemt rf power transistors require temperature-compensated gate bias voltages, similar to ldmos devices, to maintain constant quiescent drain currents with temperature. they are depletion mode dev ices requiring special bias and power sequencing compared to ldmos devices. this application note describes a bias controller module which provides these functions, and overcurrent protection. 2. bias sequencing the most important consideration for dc with gan hemts, is the bias sequencing. there are two issues to consider: ? never apply drain voltage when the gate is at 0 v, as the device draws excessive drain current. thus, any gan bias controller must include sequenced drain voltage switching. ? for a given v gs , gan hemts are likely to be potentially unstable at lower v ds . therefore, decrease the gate voltage to below the pinch-off voltage v p (such as ? 3 v) while the drain voltage is being turned on and off. figure 1 illustrates recommended power -up and power-down sequ ences for th e drain and gate voltages. (1) the typical discharge time shown is for illust ration only, and is not intended as a recommendation. it is important that v gs is held at a voltage of less than v p until v ds is less than approximately 10 v. fig 1. gate and drain voltage sequence 0 10 20 0 10 20 30 40 50 ?6 ?4 ?2 0 time (ms) v g v d 0 20 40 60 discharge through power supply aaa-001666
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 4 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 3. gate current because the gan hemt gate terminal is a sc hottky diode, bias generators must provide significant amounts of both positive and negative gate current: ? gan hemts have higher gate leakage currents than comparable ldmos devices. the negative gate current can be as high as 500 ? a/mm of gate periphery at elevated junction temperatures; the gate current evaluates to ? 5 ma for a 100 w device operating at 200 ? c junction temperature. ? when the device is driven into saturation, rectified positive gate current flows into the gate diode. at heavy rf compression, this gate current can exceed 1 ma/mm of gate periphery causing a possible gate current of 30 ma for a 100 w device. 4. temperature compensation similar to ldmos devices, the gate threshold voltage for gan devices is approximately proportional to temperature. the gate threshold voltage is the voltage required to maintain a constant quiescent drain current, which fo r nxp semiconductors gan devices, is about +1 mv/ ? c junction temperature. however, practi cal temperature compensation circuits are obliged to monitor case temperature, where the temperature change is typically only half the junction temperature change. thus, the bias controller must increase v gs by about +2 mv/ ? c. 5. summary the characteristics of the bias controller mo dule described in the following section are summarized in table 1 . [1] resistor values may have to be changed for part of range. [2] dependent upon pcb layout. table 1. summary of bias controller characteristics drain voltage 12 v to 80 v [1] gate voltage ? 3 v to ? 1 v [1] gate voltage adjustment range 700 mv typical gate voltage temperature compensation +2 mv/ ?c typical gate current, negative ? ? 10 ma gate current, positive ? 100 ma gate voltage ripple ?? 2 mv (p-p) switched drain current ? 40 a [2]
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 5 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 6. circuit description 6.1 negative voltage generation the bias controller uses a switched-capacitor voltage inverter, u1, to generate a regulated ? 4 v from a single positive supply. the +5 v s upply is generated from the high-voltage drain supply by linear regulator u4. u1 operates at a switching frequency of approximately 550 khz; c3, r4, and c10 are used to reduce output ripple to less than 2 mv (p-p). when the output voltage is within 5 % of the ? 4 v set value, the reg output goes low. the reg output low signal acts as an active -low (power valid) signal to enable drain power to the gan device. 6.2 drain voltage switching most lower power hemt bias controllers us e a p-channel power mosfet as the drain voltage load switch. this has the advantage of simplicity, often requiring nothing more than level-shifting transistors between the voltage inverter ?power valid? signal and the mosfet gate. however, as load currents increase above 2 a to 5 a, the required mosfet becomes large and expensive. cons equently, this bias controller uses a common hot-swap controller ic, u2 to drive an inexpensive n-channel mosfet. fig 2. +5 v and ? 4 v voltage generation circuit c7 1 f +5v +vd_in 8 in 1 out 5 en 2 sense gnd:4,9 u4 lt3010ems8e?5 2 c1+ 5 comp 8 shdn 6 out 1 vcc 3 c1? 7 reg gnd:4 u1 ltc1261cs8?4 c6 100 pf r9 10 k r4 10 c3 10 f c10 10 f power_valid_n ?4v c9 2.2 f c4 100 nf aaa-001667
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 6 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards u2 contains an internal charge pump for dr iving the gate of the external n-channel mosfet, qdrain. it also includes a programmable ramp-up rate, and optional overcurrent fault detection and foldback current limiting. if the voltage drop across sense resistor rsense exceeds 55 mv, u2 disconnects power fr om the drain, and leaves it latched off until power is cycled. qdrain is a low-cost high-de nsity trenchmos device in a small power so8 package. it has a typical on-resistance of less than 10 m ? and a drain current limit of more than 80 a. 6.3 temperature compensation the bias controller uses a small-signal pnp transistor (mounted in contact with the baseplate) to monitor temperature and generate a +8 mv/ ? c compensating voltage. fig 3. drain voltage load switch circuit 2 fb 1 uv 7 sense 8 vcc 5 timer 6 gate 3 pgd gnd:4 u2 lt4256?1cs8 r17 68.1 k +vd_out +vd_in r15 10 k c5 100 nf enable r3 10 k bzx385?c11 4 35 2 1 qdrain psmn8r2?80ys power_good c11 100 nf c1 10 nf r sense 0.005 55 mv/itrip r23 100 r21 75 k r22 10 aaa-001668 d4 fig 4. temperature compensating circuit aaa-001669 r19 3.01 k r7 44.2 k r18 10 k 1 3 2 qtemp bc857b vtemp ?4v
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 7 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 6.4 gate voltage adjustment a variable voltage derived from the ? 4 v supply is summed with the temperature monitor voltage to generate a temperature-compensated gate voltage. r13 and r14 are selected to set the desired gate voltage trim range, and r6 is selected to provide the desired amount of temperature compensation. figure 6 shows typical values for v gs = ? 1.6 v. u3 is a dual rail-to-rail high-current operational amplifier chosen because it is stable into any capacitive load. it can deliver more than 1 00 ma of output current to meet the positive gate current requirements of most gan hemts. fig 5. temperature compensating voltage 0102030405060708090100 ?3.5 ?3.4 ?3.3 ?3.2 ?3.1 ?3 ?2.9 ?2.8 ?2.7 ?2.6 ?2.5 baseplate temperature (c) temperature compensation voltage (v) aaa-001670
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 8 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards the output impedance of the bias source is low (less than 1 ? ) because of the feedback around operational amplifier u3. however, hemt applicatio ns usually require a series gate resistor of 5 ? to 20 ? , instead of a bias inductor, to ensure low-frequency device stability. because the gan hemt quiescent gate current can increase at high temperatures, a significant voltage drop can be developed across this gate resistor, increasing v gs by 200 mv or more. this can be a serious probl em because the increased gate voltage can push the hemt operating point into a region of instability or even cause thermal runaway. fig 6. gate voltage adjustment circuit fig 7. gate voltage 1 3 2 r18 10 k r7 44.2 k r11 100 k r19 3.01 k 1 3 2 qtemp bc857b r10 10 k r6 30.1 k ?4v 4 3 5 2 1 u3 lm7321mf c8 1 f c2 100 nf c9 1 f rg 10 r20 vgate r5 1 k r13 2 k r14 2 k 1 k aaa-001671 0102030405060708090100 baseplate temperature (c) aaa-001672 ?2 ?1.9 ?1.8 ?1.7 ?1.6 ?1.5 ?1.4 ?1.3 ?1.2 ?1.1 ?1 v g pot fully cw pot mid-scale pot fully ccw
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 9 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards one solution is to provide dc feedback from the hemt gate terminal to the operational amplifier inverting input, allowing it to compensate for voltage dropped across gate resistor rg. feedback through r20 compen sates for voltage dropped across rg. to minimize rf non-linearity and memory effects, make sure that 1 / (r20 ? c8) is less than the lowest modulation frequency of the rf signal. 6.5 resistor va lue selection the resistor values in the schematic are for a 50 v device with a nominal v gs of ? 2.1 v, +2 mv/ ? c v gs temperature coefficient, and 11 a i ds overcurrent sense. other nominal operating conditions may require resistor value changes: ? r17 determines the supply voltage at which the drain is connected. r17 = r3 (v d / 4 ? 1), so v d = 31 v with the 68.1 k ? value in the design. ? r21 determines the supply voltage at which operating v gs is applied. r21 = r15 (v d / 4.45 ? 1), so v d (good) = 38 v with the 75.0 k ? value in the design. ? rsense determines the foldback current limit. i limit = 0.055 / rsense, so i limit = 11 a with the 5 m ? value in the design. 6.6 full schematic the complete schematic of the bias contro ller combines the prec eding subcircuits with ?glue circuitry? and several (possibly optional) additional convenience features. ? leds d1 and d2 provide visual indication of valid gate and drain voltages. ? switch s1 allows the gan amplifier to be placed easily in ?standby?, where the nominal gate voltages are applied, but drain power is disconnected. ? when s1 is set to ?vd on? and the drain supply is not fully on (ramping up or down), diode d3 and mosfet q3 turn on mosfet q2, pulling the gate voltage down to ? 4v. table 2. bias module bill of materials component description value remarks c9, c12 capacitor, 100 v 10 % x7r, 1206 1 ? f c7, c8 capacitor, 50 v 10 % x7r, 0805 1 ? f c2, c4, c5, c11 capacitor, 50 v 10 % x7r, 0805 100 nf c6 capacitor, 50 v 5 % np0, 0805 100 pf c3, c10 capacitor, 10 v 20 % x7r, 0805 10 ? f c1 capacitor, 50 v 10 % x7r, 0805 10 nf d1 led, green, 0805 d2 led, yellow, 0805 d4 diode, zener 11 v 300 mw nxp bzx385-c11 d3 dual diode, common-cathode nxp bav74 l1 ferrite bead, 200 ma, 0805 1000 mh? q1, q2, q4 transistor, n-ch mos 30 v 0.8 a nxp bsh103 q3 transistor, p-ch mos 30 v 0.8 a nxp bss84 r13, r14 resistor, 1 % 100 ppm cf, 0805 2.00 k ? r5 potentiometer, 5t cermet 1 k ?
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 10 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards r19 resistor, 1 % 100 ppm cf, 0805 3.01 k ? r7 resistor, 1 % 100 ppm cf, 0805 44.2 k ? r3, r9, r10, r12, r15, r16, r18 resistor, 1 % 100 ppm cf, 0805 10.0 k ? r6 resistor, 1 % 100 ppm cf, 0805 30.1 k ? r4, r22, r24 resistor, 1 % 100 ppm cf, 0805 10.0 k ? r1, r8, r20 resistor, 1 % 100 ppm cf, 0805 1.00 k ? r17 resistor, 1 % 100 ppm cf, 0805 68.1 k ? r23 resistor, 1 % 100 ppm cf, 0805 100 k ? r2, r11 resistor, 1 % 100 ppm cf, 0805 100 k ? r21 resistor, 1 % 100 ppm cf, 0805 75.0 k ? s1 switch, spdt right-angle smd tyco 1437575-1 u4 voltage regulator, 5 v 100 ma linear lt3010ems8e-5 u1 switching capacitor inverter linear ltc1261cs8-4 u2 hot swap controller linear lt4256-1cs8 u3 rail-rail opamp national lm7321mf table 2. bias module bill of materials component description value remarks
xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx x x x xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xx xx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxx x x xxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxx xxx AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 11 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards fig 8. bias module schematic l1 blm21bd102 in en u4 lt3010ems8e?5 c9 1 f c12 1 f c7 1 f c6 100 pf c3 10 f gnd:4,9 out sense +5v 8 5 1 2 2 c1+ 8 shdn 1 vcc 3 c1? u1 ltc1261cs8?4 c2 100 nf c10 10 f r9 5 comp 6 out 7 reg gnd:4 c4 100 nf 10 k 1 2 3 bss84 q3 r4 10 r1 1 k d3 d3 baw56 baw56 r2 100 k r16 10 k r13 2 k r10 10 k r5 1 k r14 2 k 1 uv gate 8 vcc 5 timer 3 pgd 7 6 sense 2 fb gnd:4 1 3 2 q1 bsh103 1 3 2 q2 bsh103 c8 1 f c5 100 nf c11 100n c1 10 nf r3 10 k r17 68.1 k r18 10 k r7 44.2 k r19 3.01 k 1 3 2 r20 1 k r8 1 k r12 10 k r6 30.1 k 7 8 9 c temperature b compensation e npn transistor 5 6 4 3 2 1 v+ d drain g switching s npn mosfet 10 11 12 vg fb r11 100 k 1 32 q4 bsh103 -4v 4 3 5 2 1 u3 lm7321mf r22 10 r21 75 k r23 100 r15 10 k 2 1 3 3 r24 10 1 2 3 v d on s1 1437575?1 standby d4 bzx384-c11 d1 hsmg?c170 green = v g on d2 hsmy?c170 yellow = v d on u2 lt4256-1cs8 aaa-001673
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 12 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 7. pcb layout 8. abbreviations fig 9. pcb top-side layout aaa-001674 fig 10. pcb bottom-side layout aaa-001675 table 3. abbreviations acronym description ldmos laterally diffused metal oxide semiconductor mosfet metal oxide semiconductor field effect transistor
AN11130 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2011. all rights reserved. application note rev. 1 ? 8 december 2011 13 of 14 nxp semiconductors AN11130 bias module for 50 v gan demonstration boards 9. legal information 9.1 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. 9.2 disclaimers limited warranty and liability ? information in this document is believed to be accurate and reliable. however, nxp semiconductors does not give any representations or warranties, expressed or implied, as to the accuracy or completeness of such information and shall have no liability for the consequences of use of such information. in no event shall nxp semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or replacement of any products or rework charges) whether or not such damages are based on tort (including negligence), warranty, breach of contract or any other legal theory. notwithstanding any damages that customer might incur for any reason whatsoever, nxp semiconductors? aggregate and cumulative liability towards customer for the products described herein shall be limited in accordance with the terms and conditions of commercial sale of nxp semiconductors. right to make changes ? nxp semiconductors reserves the right to make changes to information published in this document, including without limitation specifications and product descriptions, at any time and without notice. this document supersedes and replaces all information supplied prior to the publication hereof. suitability for use ? nxp semiconductors products are not designed, authorized or warranted to be suitable for use in life support, life-critical or safety-critical systems or equipment, nor in applications where failure or malfunction of an nxp semiconductors product can reasonably be expected to result in personal injury, death or severe property or environmental damage. nxp semiconductors accepts no liability for inclusion and/or use of nxp semiconductors products in su ch equipment or applications and therefore such inclusion and/or use is at the customer?s own risk. applications ? applications that are described herein for any of these products are for illustrative purpos es only. nxp semiconductors makes no representation or warranty that such applications will be suitable for the specified use without further testing or modification. customers are responsible for the design and operation of their applications and products using nxp semiconducto rs products, and nxp semiconductors accepts no liability for any assistance wi th applications or customer product design. it is customer?s sole responsibility to determine whether the nxp semiconductors product is suitable and fit for the customer?s applications and products planned, as well as fo r the planned application and use of customer?s third party customer(s). customers should provide appropriate design and operating safeguards to minimize the risks associated with their applications and products. nxp semiconductors does not accept any liability related to any default, damage, costs or problem which is based on any weakness or default in the customer?s applications or products, or the application or use by customer?s third party customer(s). customer is responsible for doing all necessary testing for the customer?s applic ations and products using nxp semiconductors products in order to av oid a default of the applications and the products or of the application or use by customer?s third party customer(s). nxp does not accept any liability in this respect. export control ? this document as well as the item(s) described herein may be subject to export control regulations. export might require a prior authorization from competent authorities. evaluation products ? this product is provided on an ?as is? and ?with all faults? basis for evaluati on purposes only. nxp semico nductors, its affiliates and their suppliers expressly disclaim all warranties, whether express, implied or statutory, including but not limited to the implied warranties of non-infringement, merchantability and fitness for a particular purpose. the entire risk as to the quality, or arising out of the use or performance, of this product remains with customer. in no event shall nxp semiconductors, its affiliates or their suppliers be liable to customer for any special, indirect, consequential, punitive or incidental damages (including without limitation damages for loss of business, business interruption, loss of use, loss of data or information, and the like) arising out the use of or inability to use the product, whether or not based on tort (including negligence), strict liability, breach of contract, breach of warranty or any other theory, even if advised of the possibility of such damages. notwithstanding any damages that customer might incur for any reason whatsoever (including without limitat ion, all damages referenced above and all direct or general damages), the entire liability of nxp semiconductors, its affiliates and their suppliers and custom er?s exclusive remedy for all of the foregoing shall be limited to actual damages incurred by customer based on reasonable reliance up to the greater of the amount actually paid by customer for the product or five dollars (us$5.00) . the foregoing limitations, exclusions and disclaimers shall apply to the ma ximum extent permitted by applicable law, even if any remedy fails of its essential purpose. 9.3 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners.
nxp semiconductors AN11130 bias module for 50 v gan demonstration boards ? nxp b.v. 2011. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 8 december 2011 document identifier: AN11130 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 10. contents 1 introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 2 bias sequencing . . . . . . . . . . . . . . . . . . . . . . . . 3 3 gate current . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 4 temperature compensation . . . . . . . . . . . . . . . 4 5 summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 circuit description . . . . . . . . . . . . . . . . . . . . . . . 5 6.1 negative voltage generation . . . . . . . . . . . . . . . 5 6.2 drain voltage switching. . . . . . . . . . . . . . . . . . . 5 6.3 temperature compensation . . . . . . . . . . . . . . . 6 6.4 gate voltage adjustment. . . . . . . . . . . . . . . . . . 7 6.5 resistor value selection . . . . . . . . . . . . . . . . . . 9 6.6 full schematic. . . . . . . . . . . . . . . . . . . . . . . . . . 9 7 pcb layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 8 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 12 9 legal information. . . . . . . . . . . . . . . . . . . . . . . 13 9.1 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.2 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 9.3 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 13 10 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14

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